HP has unveiled research it says could lead to the creation of field programmable gate arrays up to eight times denser – while using less energy – than those currently being produced.
The company said the chips could be built using the same sized transistors as those used in current FPGA design, meaning they could be built in current fabrication facilities with only minor modifications.
FPGAs are integrated circuits with programmable logic components and interconnects that can be adapted by end-users for specific applications. They are used in a wide range of industries, including communications, automotive and consumer electronics.
The technology calls for a nanoscale crossbar switch structure to be layered on top of conventional CMOS (complementary metal oxide silicon), using an architecture HP Labs researchers have named “field programmable nanowire interconnect (FPNI)” – a variation on the well-established FPGA technology.
“As conventional chip electronics continue to shrink, Moore’s Law is on a collision course with the laws of physics,” said Stan Williams, an HP Senior Fellow and director, Quantum Science Research, HP Labs. “Excessive heating and defective device operation arise at the nanoscale. What we’ve been able to do is combine conventional CMOS technology with nanoscale switching devices in a hybrid circuit to increase effective transistor density, reduce power dissipation, and dramatically improve tolerance to defective devices.”
